Field of the Invention
This invention relates to biasing of distributed amplifier monolithic microwave integrated circuits (MMICs), and more particularly to an off-chip DC bias circuit for distributed drain biasing of a high power distributed amplifier MMIC.
Description of the Related Art
A Monolithic Microwave Integrated Circuit, or MMIC, is a type of integrated circuit (IC) device that operates at microwave frequencies (300 MHz to 300 GHz). These devices typically perform functions such as microwave mixing, power amplification, low-noise amplification, and high-frequency switching. Inputs and outputs on MMIC devices are frequently matched to a characteristic impedance of 50 ohms. This makes them easier to use, as cascading of MMICs does not then require an external matching network. Additionally, most microwave test equipment is designed to operate in a 50-ohm environment.
MMICs are dimensionally small (from around 1 mm2 to 20 mm2) and can be mass-produced, which has allowed the proliferation of high-frequency devices such as cellular phones. MMICs were originally fabricated using gallium arsenide (GaAs), a III-V compound semiconductor. It has two fundamental advantages over silicon (Si), the traditional material for IC realization: device (transistor) speed and a semi-insulating substrate. Both factors help with the design of high-frequency circuit functions. However, the speed of Si-based technologies has gradually increased as transistor feature sizes have reduced, and MMICs can now also be fabricated in Si technology. Other technologies such as indium phosphide (InP), Silicon germanium (SiGe) and Gallium nitride (GaN) are also options for MMICs. Originally, MMICs used MEtal-Semiconductor Field-Effect Transistors (MESFETs) as the active device. More recently High Electron Mobility Transistors (HEMTs), Pseudomorphic HEMTs and Heterojunction Bipolar Transistors have become common.
DC bias circuitry typically occupies about 15% to 20% of the total chip area. DC bias circuitry may function as both a DC power supply path to transistors and an RF block (“bias choke”). In high power applications, such as the MMIC, the DC bias circuitry typically employs wide transmission lines to accommodate the large current flow to transistors. On-chip capacitors are configured for providing an RF choke. The high impedance transmission line acts as a virtual open to the RF signals, and the on-chip capacitors are configured to short residual RF signals to ground.
U.S. Pat. No. 6,798,313 entitled “Monolithic Microwave Integrated Circuit with Bondwire and Landing Zone Bias” issued Sep. 28, 2004 discloses an approach for moving the DC bias circuitry off-chip such that on-chip bias circuitry can be reduced and/or eliminated. In an embodiment of a multi-stage RF power amplifier, which amplifies RF signals over a narrowband e.g., 10% of the central frequency, a bondwire is attached between a landing zone located at a suitable location on the MMIC to supply bias current and an off-chip capacitor. The bondwire may be configured to provide the RF impedance that was provided by the on-chip bias circuitry. The bond wire may be configured to have any suitable length to create a virtual open. The bond wire length may then suitably depend on the frequency being blocked. For example, the bond wire may be selected to be a quarter-wave bond wire. The length of an exemplary bond wire may be about 100 mils for a 30 GHz signal. In this case, the length of the bond wire may have a tolerance of, for example, plus or minus 30 mils. The off-chip bias feed system may thus be configured to not significantly impact the overall RF impedance of the system by placing a high RF impedance bond wire in parallel with a low RF impedance matching structure.
Another class of MMIC amplifiers is a distributed amplifier, which amplifies RF signals over a much wider bandwidth (e.g. at least 120% of the central frequency) with less gain than a multi-stage power amplifier to obtain a larger gain-bandwidth product. Distributed amplifiers use transmission lines to temporally split the signal and amplify each portion separately to achieve higher bandwidth than possible from a single amplifier. The outputs of each stage are combined in the output transmission line. The distributed amplifier includes a pair of transmission lines with characteristic impedances of Z0 independently connecting the inputs and outputs of several active devices (e.g., FETs). An RF signal is thus supplied to the section of transmission line connected to the input of the first device. As the input signal propagates down the input line, the individual devices respond to the forward traveling input wave by inducing an amplified complementary forward traveling wave on the output line. This assumes the delays of the input and output lines are made equal through selection of propagation constants and lengths of the two lines and as such the output signals from each individual device sum in phase. Terminating resistors Zg and Zd are placed to minimize destructive reflections. The transconductive gain of each device is gm and the output impedance seen by each transistor is half the characteristic impedance of the transmission line. So that the overall voltage gain is: Av=½n·gm·Z0, where n is the number of stages. Neglecting losses, the gain demonstrates a linear dependence on the number of devices (stages). Unlike the multiplicative nature of a cascade of conventional amplifiers, the distributed amplifier demonstrates an additive quality. It is this synergistic property of the architecture that makes it possible for it to provide gain at frequencies beyond that of the unity-gain frequency of the individual stages. In practice, the number of stages is limited by the diminishing input signal resulting from attenuation on the input line.
DC bias circuitry for a MMIC distributed amplifier chip is configured to provide DC bias current at the drain connection of the last transistor (stage). High power amplifiers use a tapered drain line. The 1st stage FET is connected to a skinny line (high impedance) and each succeeding stage has a wider line connecting it. The last FET stage has widest line and the lowest impedance, which provides a good location to place a high impedance choke to bring the DC current into the amplifier. The line width is at a maximum so the current carrying capability of the line is at a maximum and the circuit is the least disturbed by the choke at this point. The bias current is supplied to all of the transistors (stage) as required through the output line.
The DC bias circuitry comprises a series inductor L connected to a grounded capacitor C. The inductor L provides an RF open that blocks signal from being shunted to the bias circuitry and a DC short that allows bias current to flow to the chip. The capacitor provides a DC open that blocks DC current from being shunted to ground and an RF short that allows RF from the bias circuitry to flow to ground to avoid injecting RF noise into the amplifier.
The DC bias circuitry may be provided on-chip for low power distributed amplifiers or off-chip for high power amplifiers. An on-chip inductor is a critical design element and tends to set the performance at the frequency band edges. An inductive line at the low-end of the band tends to look capacitive at the high-end and rolls off RF performance. A bias line suitable for the high-end of the band hurts performance at the low-end. Higher power amplifiers tend to make on-chip bias chokes difficult or impossible to achieve due to the increased line-widths required to handle the higher DC currents. Off-chip inductors (e.g., wire-wound inductors) allow for physically smaller MMICs and can provide the inductance required for higher power distributed amplifiers.